1. Field of the Invention
The present invention relates to a failure analyzer for analyzing the cause of failures of a semiconductor device, and more particularly to an improvement of obtaining coordinate values of defects having high precision and enhancing precision of analysis.
2. Description of the Background Art
A method using a tester (which is also referred to as a LSI tester) has been known as a method for analyzing failures of a semiconductor wafer on which a plurality of semiconductor chips are formed, each semiconductor chip having a plurality of memory cells (generally arranged in a matrix of rows and columns). According to this method, a test of electrical characteristics is performed for all the memory cells in the semiconductor wafer, failures detected as a result of the test are displayed in the form of a failure pattern (generally referred to as a fail bit map (FBM)) in a coordinate space defined by a longitudinal x-coordinate and a transverse y-coordinate, and the cause of failures is estimated by using the FBM.
Although a three-dimensional position of a failure and a knowledge of electrically abnormal phenomena thereon, that is, a knowledge of failure phenomena that anything (leakage/open/short circuit, etc.) is caused in any place are directly obtained by the FBM, the cause of failures is not indicated directly. On the site of manufacture or checks, the FBM is not enough to improve failed portions. Therefore, it is necessary to make the cause of the failure phenomena in manufacturing process clear.
A method proposed on the basis of such a thought has been disclosed in Japanese Unexamined Patent Publication No. 6-275688. According to this method, a defect checking device is used to obtain the results of a physical check such as foreign substances, defects and the like on a surface of a semiconductor wafer for each step of a manufacturing line (these abnormalities which might be the cause of failures are represented by "defects" in this specification). At the same time, a test of electrical characteristics is performed, by using a tester, for each memory cell of the semiconductor wafer manufactured through the manufacturing line. A FBM obtained on the basis of results of the test is collated with the results of the physical check related to the defects for each step. Consequently, it is estimated whether the failures are caused by defects generated at each manufacturing step or not.
The results of the check are collated with the FBM by retrieving, for each step, defects existing in a predetermined tolerance around each failure belonging to the FBM which are obtained by the defect checking device. If the tolerance has a proper size, it is estimated that the defects existing in the tolerance are the cause of failures. If a position of each failure of the FBM is closer to that of the defect obtained by the defect checking device, there is a higher possibility that the defect might be the cause of the failure.
If precision of the position of the defect is sufficiently high, the position of each failure of the FBM is ideally coincident with that of the defect which causes the failure. However, the results of the check vary from one to another in the form of data and in the precision of the position of the defect for each defect checking device to be used at each step. For example, the precision of the position of the defect is reflected by precision of a position of a stage on which the semiconductor wafer to be checked is mounted, and the like.
It is necessary to increase the tolerance for the results of a check having low precision of a position. For this reason, reliability of a collation is lowered. In the case where results of a check having high precision of a position and those of a check having low precision of a position are collated in the same processing, a tolerance should be adapted to poor precision of the position. Therefore, the reliability is wholly lowered. FIGS. 28 and 29 are diagrams for explaining these circumstances.
As shown in FIG. 28, a point failure 20 acting as one of FBMs and a defect 23 in an x-y coordinate system are collated with each other by retrieving the defect 23 existing in a tolerance r1 (or r2) from the point failure 20. More specifically, the defect 23 existing in a circular region 21 (or 22) having the point failure 20 as a center and the tolerance r1 (or r2) as a radius is retrieved. At this time, the tolerance r1 for a collation with the results of a check obtained by a defect checking device having high precision of a position and the tolerance r2 for a collation with the results of a check obtained by a defect checking device having low precision of a position have the following relationship. EQU r1&lt;r2 (1)
As shown in FIG. 29, a line failure 25 which replaces the point failure is collated with the defect 23 by retrieving the defect 23 existing in the tolerance r1 (or r2) from the line failure 25. More specifically, the defect 23 existing in a region 26 (or 27) in which a distance from the line failure 25 is within the tolerance r1 (or r2) is retrieved. Accordingly, if a tolerance is set widely corresponding to low precision of a position, the defect 23 which is not related to the point failure 20 or the line failure 25 is collated. As a result, reliability of results of a collation, that is, precision of analysis of the cause of failures is lowered.
If the precision of a position of a defect is not good and a coordinate value of the defect having high precision can be obtained by proper correction, the reliability of the results of a collation can be enhanced and the defect can quickly be found and analyzed by using the coordinate value of the defect for another analyzer such as a SEM (scanning electron microscope) to which a coordinate linkage function is added.